Wireless communication devices, such as mobile phone handsets, require a very high level of integration of hardware and firmware/software in order to achieve the necessary density of functionality, i.e. to realise the necessary functionality in a minimum device volume and at a minimum cost. An optimal wireless communication device design must also minimise power consumption in order to increase the battery call time and/or stand-by time.
Wireless communication devices also incorporate a number of distinct and operably coupled sub-systems, in order to provide the wide variety of functions and operations that a complex wireless communication device needs to perform. Such sub-systems comprise radio frequency power amplification functions, radio frequency integrated circuits (RFIC) comprising radio frequency generation, amplification, filtering logic, etc. as well as baseband integrated circuits (BBIC) comprising audio circuits, encoding/decoding, (de)modulation functions, processing logic, etc. and memory units.
Interfaces, which are often standardised to allow commonality and increased functionality between different chip-set manufacturers and different handset manufacturers, are defined for communicating between the respective sub-systems.
In the field of mobile phones, a consortium of mobile phone manufacturers has been formed to define various sub-system interfaces, particularly interfaces for variants of the second generation (2x.G), third generation (3G) and fourth generation (4G) of cellular phones comprising communication technologies such as multimode transceivers additionally employing different access technologies such as wideband code division multiple access (WCDMA). This consortium is known as ‘DigRF’ and details of the defined interfaces and functionality thereof, particularly in a multimode mobile phone scenario, can be found on their web-site at www.digrf.com. One interface being defined by the DigRF consortium is the Dual-Mode 2.5G and 3G interface baseband (BB)-radio frequency (RF) interface standard, which encompasses a serial interface for Control, Receive (Rx) and Transmit (Tx) variants of cellular phones chipsets. The Dual-Mode 2.5G and 3G interface is implemented using differential voltage pairs for data transfers.
Within 3G DigRF, the transmit data is referred to as ‘TxData’ in the direction from the BBIC to the RFIC and the receive data is referred to as ‘RxData’ routed in the direction from the RFIC to the BBIC. The RFIC-BBIC interface supports the following data rates:                (i) TxData: Low speed at SysClk/4 and High speed at 312 Mbps, and        (ii) RxData: Low speed at SysClk/4 and SysClk, and High speed at 312 Mbps, where SysClk (i.e. the system clock) may operate at 19.2 MHz, 26 MHz or 38.4 MHz.        
Data transmission between the baseband (BB) line drive and RF line receiver is asynchronous in nature. Consequently, the uplink controller does not have the knowledge about the correct clock phase to be used for extracting the data. Thus, a synchronization pattern is transmitted close to the start of a frame to facilitate synchronization, and cross-correlation algorithms are used to determine the best clock phase for extraction of data. As a result, synchronization and cross-correlation activities are key functions of the interface.
The receiving end of the Dual-Mode 2.5G and 3G interface is required to provide a means of adjusting the sample phase of the selected clock speed (which may be running at 1248 MHz or 2496 MHz for high speed) so as to centre the sampling point in the centre the data bit period, as understood by those skilled in the art, and hence ensure reliable communication. The Dual-Mode 2.5G and 3G interface Standard suggests the use of eight nominally equally-spaced 312 MHz sample phases (in practice approximately 45 degrees separated) each within a bit period for high speed data rates. The Dual-Mode 2.5G and 3G interface standard also proposes a low power mode whereby every other phase is skipped in the sampling logic, thereby allowing the receiver to operate using only four phase samples for high and low speed data rates. For low data rates (SysClk/4) 4 equally spaced samples phases (SysClk) can be used.
There are a number of known methods that may be used to sample the low or high speed data arriving on the Dual-Mode 2.5G and 3G interface. For example, over-sampling the data with a higher clock speed and/or over-sampling the data with a number of clock phases may be used. These over-sampling techniques are known to require very fast clock rates, whereby many functions significantly affect the fine margins in ensuring the correct clock signal is applied to the correct logic element at the correct time instant. For example, if over-sampling is applied to the eight nominally equally-spaced 312 MHz sample phases, the transition time between sampling phase ‘7’ and phase ‘0’ are adversely affected by, say, propagation factors of an integrated circuit layout, clock jitter, a number of logic components in the clock generation and routing path, etc. In such a situation, it is very difficult to ensure correct operation of sample and hold circuits, such as flip-flops, registers, etc., that is to ensure the correct data signal is input to the sample and hold circuit when the correct clock phase trigger is applied, particularly when high speed data is to be supported.
In general, when designing integrated circuits to support communications across an interface, a digital circuit designer has to take into account many factors that affect the performance of the manufactured integrated circuit. For example, known limitations with digital circuit design further encompass accommodating sampling techniques to operate across multiple data rates and clock rates (or clock phases being used), thereby increasing the complexity of the clock tree design.
Thus, it is often advantageous to reduce the clock tree complexity, namely the generation and propagation of respective clock signals as they are divided/multiplied from a clock source and routed around the digital circuits.
A need therefore exists for an improved electronic device and method to sample data, particularly in the context of a Dual-Mode 2.5G and 3G interface wireless communication device and integrated circuit therefor, without incurring increased cost, power, silicon area or complexity.